EDN

SystemVerilog reference verification methodology: Introduction

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. Traditional verification methods struggle to keep pace with the ever-increasing size ...
Business Wire

Cadence and Mentor Graphics Deliver Interoperability with Open SystemVerilog Verification Methodology

SAN JOSE, Calif., & WILSONVILLE, Ore.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ:CDNS), and Mentor Graphics Corp. (NASDAQ:MENT) today announced that they will standardize on a verification ...
Electronic Design

EDA> Design And Verification Evolves With SystemVerilog

SystemVerilog is the natural evolution of the Verilog language, extending its capabilities for both design and verification. Demand for this advanced language is clear. Over a dozen EDA companies ...
Electronic Design

SystemVerilog Verification Reaches For Higher Productivity

In its continuing efforts to harness the considerable verification power of SystemVerilog, Synopsys has rolled out extensions to the verification methodology spelled out in its System Verilog ...
Semiconductor Engineering

Simplifying SystemVerilog Functional Coverage

Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is ...
Business Wire

IEEE Publishes Standard Revision for SystemVerilog – Unified Hardware Design, Specification and Verification Language

PISCATAWAY, N.J.--(BUSINESS WIRE)--IEEE, the world's largest technical professional organization dedicated to advancing technology for humanity, and the IEEE Standards Association (IEEE-SA), today ...
Semiconductor Engineering

Find Bugs Early: On-The-Fly Code Correction For Design And Verification Productivity

The key rule for chip design and verification is that bugs must be found and fixed as early in the development process as possible. It is often said that catching a bug at each successive project ...
Design News

What is the Difference Between Test and Verification?

People freely interchange the terms “test” and “verification.” It’s understandable when terms like testcase, testbench and device under test (DUT) are in conjunction with different types of ...
EDN

SystemVerilog reference verification methodology: RTL

The SoC industry needs a reuse-oriented, coverage-driven verification methodology built on the rich semantic support of a standard language. This is the second in a series of four articles outlining a ...